| Feature | Specification | Benefit |
|---|---|---|
| Power Consumption | 55 nW (static) / 80 nW max | 10+ year battery life for edge/IoT devices |
| Silicon Area | <0.05 mm² (28nm) | Fits in any sensor or MCU — zero cost barrier |
| Logic Gate Count | Exactly 5,357 gates | Ultra-low manufacturing cost, high yield |
| Key Storage | 100% stateless (no NVM) | Immune to physical key extraction |
| Healing Mechanism | Invariant Q = (w - k)G | Post-compromise identity recovery |
| Operation Mode | 100% offline / air-gapped | No cloud dependency, no network attack surface |
| Integration | RTL drop-in (Verilog) | Rapid integration into existing SoC/ASIC flows |
Automatically rotates hardware identity upon tamper detection. No recalls needed.
No master keys stored. Every authentication is fresh, ephemeral, and non-replayable.
Add Anti-Cloning Counter (+200g), Security Heartbeat (+300g), or Kill-Switch (+150g).
Synthesis scripts and timing constraints included for 40nm/22nm FD-SOI processes.
Cell-level identity, anti-counterfeit, firmware hijack protection
Zero-trust anti-cloning, hardware kill-switch for EV networks
10-year security heartbeat on energy-harvested power
Offline, proximity-based authentication for pacemakers, pumps
Root of Trust for neural network weights, model IP protection
Stateless identity — post-capture integrity, anti-spoofing
Non-exclusive IP licensing available for semiconductor manufacturers, automotive OEMs, and security IP integrators.
✓ RTL complete and verified · Ready for immediate tape-out integration